Integrated circuit chip manufacturers fabricate advanced semiconductor devices by different combinations of processes such as sequentially forming metals, oxides, doped semiconductor, and other materials in layers usually thinner than 1 .mu.m thick and, then, etching away predetermined portions of the thin films from the semiconductor wafer. In these techniques, manufacturing process control and fabrication tolerance are important considerations. Moreover, as the integrated circuit packing density and chip size increase with each new technology generation, ensuring process control and satisfying fabrication tolerances become even more important requirements. Many conventional fabrication techniques and device structures, however, cannot easily meet these requirements.
One important aspect of forming semiconductor devices is the ability to electrically isolate each active component from other active components on the integrated circuit. While this is a critical consideration in Very-Large-Scale Integrated (VLSI) circuits and Ultra-Large-Scale Integrated (ULSI) circuits, traditional isolation structures are not easily scalable for use in sub-half-micron VLSI and ULSI technologies. There are numerous reasons why the conventional isolation techniques have not proven scalable down to the sub-half-micron regimes. For example, the widely used isolation method known as local oxidation of silicon (LOCOS) is a device isolation technique used to form isolation structures in integrated circuit devices. The LOCOS isolation, however, suffers from a limitation known as the formation of what is often called "bird's beak" regions at the isolation edge regions on the device. For example, FIG. 1 illustrates a conventional transistor device structure 10 that has a LOCOS-related bird's beak typical of most LOCOS-type isolation methods. Semiconductor device 10 uses silicon substrate 12 on which appears transistor gate structure 14 and silicon dioxide LOCOS isolation structures 16 over the field channel stop regions 18. Gate structure 14 includes gate electrode 20, gate dielectric 22 and spacers 24 over n-type lightly doped drain (LDD) 26 regions. The n-type LDD regions 26 are connected to the heavily doped source/drain junctions 28.
As FIG. 1 clearly illustrates, bird's beak 30 has associated bird's beak length, L.sub.BB, which is defined by the field oxide region between the point 32 at which the field oxide thickness begins to decrease and the final point 34 adjacent the source/drain junctions 28. Bird's beak (30) forms a transition region of length L.sub.BB between the field isolation region and the active device region that is essentially non-usable in the device. The LOCOS-related bird's beak regions 30 result in the reduced device packing density due to the loss of a fraction of the substrate area available for circuit layout. Additionally, excessive diffusion and spread of the channel-stop implant 18 occurs and non-planar surface for device 10 results due to the thermal oxidation process used in the LOCOS-based isolation techniques.
FIG. 2 shows how a conventional LOCOS process forms the bird's beak regions. On semiconductor structure 11 appears LOCOS oxidation mask 13 that comprises a chemical-vapor-deposited silicon nitride layer 15 (oxidation mask) over a pad oxide layer 17. The pattern oxide mask 15 is used as an oxidation mask over substrate 12 and also masks the implantation of boron performed to form self-aligned channel stop regions 18. During a steam oxidation process after formation of the patterned LOCOS oxidation mask layer 15, patterned oxidation mask 13 protects a portion of silicon substrate 12 against thermal oxidation, while the remaining portions of substrate 12 (which have been implanted with channel-stop boron) form conventional field oxide isolation structure 16. Because this method employs a thermal oxidation process, the thermally grown field oxide layer penetrates underneath the patterned LOCOS mask 13 edge. As a result, LOCOS bird's beak regions 30 arise as an extended region beneath patterned LOCOS mask 13 (also resulting in the lifting of the nitride mask layer 15).
FIGS. 3a and 3b very simply show another phenomenon that occurs due to bird's beak formation that limits the usefulness of conventional LOCOS and modified LOCOS techniques. For example, given that a desired field isolation silicon oxide thickness may be 7000 .ANG. such as shown in FIG. 3a, as the lateral dimension or width W of isolation structure 40 decreases (e.g., due to technology sealing) to the width W' as shown in FIG. 5b, the LOCOS-induced mechanical stresses and bird's beak regions cause a thinning of the maximum isolation field oxide thickness to below 7000 .ANG. for a given thermal oxidation cycle. This is due to the fact that the LOCOS-induced stresses at the field corners reduce the overall field oxide thickness below the desired wide field values when the lateral field oxide isolation dimensions are scaled down to the sub-micron regime. This places a limit on the scaling of LOCOS type structures.
To overcome these problems, numerous alternative modified LOCOS techniques have been proposed. These include Sealed Interface LOCOS (SILO) and Poly-Buffered LOCOS (PBL) techniques, which are modified LOCOS techniques that seek to provide more scalable isolation structures which reduce the bird's beak phenomenon. Other modified LOCOS techniques have been suggested which employ a shallow silicon trench etch to form more planar isolation structures. This planarity, however, is obtained at the cost of increased stress-induced defect density in silicon. In general, these modified LOCOS techniques can produce a more planar isolation structure, but they result in higher active device stresses and more stress-induced defects in the transistor device regions. Also, they are not fully effective to eliminate the bird's beak problem.
Consequently, there is a need for an improved method to fabricate integrated circuit isolation structures that is not only scalable well into the sub-micron regime, but also avoids the bird's beak and stress problems of conventional LOCOS isolation techniques. In particular, the lateral dimensions of the isolation structure should be easily scalable to the critical dimensions of lithography resolutions limits for the sub-micron semiconductor device structures.
There is a need for a method and structure that avoid electrically-active defects in active device regions of integrated circuits. And, there is a need for an improved semiconductor device isolation structure fabrication process that can produce stress-free and defect-free active silicon regions.
There is a need for a fabrication method and structure which can produce device isolation structures with high-quality isolation/substrate interface regions for effective device-to-device electrical isolation at minimum isolation dimensions.
There is a further need for a method and structure to form integrated circuit isolation regions that avoids field-oxide thinning problems of conventional LOCOS techniques. Thus, as the lateral dimensions of the isolation regions are scaled down, there is a need for a method and structure that avoids the field-oxide thinning effects.